# Pastebin x1R1kO3d
\section{Instruction set}
\subsection{Core instructions}

\begin{tabular}{ |l|l| }
  \hline
  \multicolumn{2}{|c|}{BMIU core microcode instruction set} \\
  \hline
\textbf{IM} & Push immediate number onto stack \\
\textbf{FM} & Fetch memory onto stack \\
\textbf{LM} & Load memory from stack \\
\textbf{CP} & Complete procedure \\
  \hline
\end{tabular}

The BMIU architecture consists of an inner and outer control unit. The inner control unit operates on microcode located in the first 1K of memory between address $0000 and $04FF. The outer control unit reads from the memory address of the 16 bit program counter at $600, obtaining a pointer to microcode stored in the in memory programmable decoder at address $0500 - $05FF. The offset of the decoder memory is the value retrieved from the address pointed to by the Instruction Pointer register.