# Pastebin mIV2rcfS
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   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Oct 13 2020 13:09:50
 BIOS CRC passed (488e6e03)

 Migen git sha1: --------
 LiteX git sha1: 15dc9747

--=============== SoC ==================--
CPU:		VexRiscv @ 200MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		32KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		1048576KiB 64-bit @ 1600MT/s (CL-11 CWL-9)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  Cmd/Clk scan:
  |00000000  |0000  |0000  |0000| best: -1
  Setting Cmd/Clk delay to -1 taps.
  Data scan:
  m0: |00000000001111111111100001| delay: 157
  m1: |00000000001111111111000001| delay: 145
  m2: |00000001111111111000000001| delay: 97
  m3: |00111111111111000000000000| delay: 32
  m4: |11000000000000111111111111| delay: 209
  m5: |11111110000000000011111110| delay: 285
  m6: |11111111100000000000011110| delay: -
  m7: |11111111111111111111111111| delay: -
Write latency calibration:
m0:0 m1:0 m2:0 m3:0 m4:6 m5:0 m6:0 m7:0 
Read leveling:
  m0, b0: |00000000000000000000000000000000| delays: -
  m0, b1: |00000000000000000000000000000000| delays: -
  m0, b2: |00000000000000000000000000000000| delays: -
  m0, b3: |00000000000000000000000000000000| delays: -
  m0, b4: |00000000000000000000000000000000| delays: -
  m0, b5: |00000000000000000000000000000000| delays: -
  m0, b6: |00000000000000000000000000000000| delays: -
  m0, b7: |00000000000000000000000000000000| delays: -
  best: m0, b00 delays: -
  m1, b0: |00000000000000000000000000000000| delays: -
  m1, b1: |00000000000000000000000000000000| delays: -
  m1, b2: |00000000000000000000000000000000| delays: -
  m1, b3: |00000000000000000000000000000000| delays: -
  m1, b4: |00000000000000000000000000000000| delays: -
  m1, b5: |00000000000000000000000000000000| delays: -
  m1, b6: |00000000000000000000000000000000| delays: -
  m1, b7: |00000000000000000000000000000000| delays: -
  best: m1, b00 delays: -
  m2, b0: |00000000000000000000000000000000| delays: -
  m2, b1: |00000000000000000000000000000000| delays: -
  m2, b2: |00000000000000000000000000000000| delays: -
  m2, b3: |00000000000000000000000000000000| delays: -
  m2, b4: |00000000000000000000000000000000| delays: -
  m2, b5: |00000000000000000000000000000000| delays: -
  m2, b6: |00000000000000000000000000000000| delays: -
  m2, b7: |00000000000000000000000000000000| delays: -
  best: m2, b00 delays: -
  m3, b0: |00000000000000000000000000000000| delays: -
  m3, b1: |00000000000000000000000000000000| delays: -
  m3, b2: |00000000000000000000000000000000| delays: -
  m3, b3: |00000000000000000000000000000000| delays: -
  m3, b4: |00000000000000000000000000000000| delays: -
  m3, b5: |00000000000000000000000000000000| delays: -
  m3, b6: |00000000000000000000000000000000| delays: -
  m3, b7: |00000000000000000000000000000000| delays: -
  best: m3, b00 delays: -
  m4, b0: |01111111111000000000000000000000| delays: 89+-70
  m4, b1: |00000000000000000000000000000000| delays: -
  m4, b2: |00000000000000000000000000000000| delays: -
  m4, b3: |00000000000000000000000000000000| delays: -
  m4, b4: |00000000000000000000000000000000| delays: -
  m4, b5: |00000000000000000000000000000000| delays: -
  m4, b6: |00000000000000000000000000000000| delays: -
  m4, b7: |00000000000000000000000000000000| delays: -
  best: m4, b00 delays: 89+-71
  m5, b0: |00000000000000000000000000000000| delays: -
  m5, b1: |00000000000000000000000000000000| delays: -
  m5, b2: |00000000000000000000000000000000| delays: -
  m5, b3: |00000000000000000000000000000000| delays: -
  m5, b4: |00000000000000000000000000000000| delays: -
  m5, b5: |00000000000000000000000000000000| delays: -
  m5, b6: |00000000000000000000000000000000| delays: -
  m5, b7: |00000000000000000000000000000000| delays: -
  best: m5, b00 delays: -
  m6, b0: |00000000000000000000000000000000| delays: -
  m6, b1: |00000000000000000000000000000000| delays: -
  m6, b2: |00000000000000000000000000000000| delays: -
  m6, b3: |00000000000000000000000000000000| delays: -
  m6, b4: |00000000000000000000000000000000| delays: -
  m6, b5: |00000000000000000000000000000000| delays: -
  m6, b6: |00000000000000000000000000000000| delays: -
  m6, b7: |00000000000000000000000000000000| delays: -
  best: m6, b00 delays: -
  m7, b0: |00000000000000000000000000000000| delays: -
  m7, b1: |00000000000000000000000000000000| delays: -
  m7, b2: |00000000000000000000000000000000| delays: -
  m7, b3: |00000000000000000000000000000000| delays: -
  m7, b4: |00000000000000000000000000000000| delays: -
  m7, b5: |00000000000000000000000000000000| delays: -
  m7, b6: |00000000000000000000000000000000| delays: -
  m7, b7: |00000000000000000000000000000000| delays: -
  best: m7, b00 delays: -
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
  Write: 0x40000000-0x40200000 2MiB     
   Read: 0x40000000-0x40200000 2MiB     
  bus errors:  208/256
  addr errors: 5136/8192
  data errors: 524288/524288
Memtest KO
Memory initialization failed