# Pastebin lX3Ybxeu
steev@flex5g:~$ dmesg | grep mmu
[    0.086785] iommu: Default domain type: Translated
[    0.086802] iommu: DMA domain TLB invalidation policy: strict mode
[    0.248323] arm-smmu 15000000.iommu: probing hardware configuration...
[    0.248345] arm-smmu 15000000.iommu: SMMUv2 with:
[    0.248401] arm-smmu 15000000.iommu:         stage 1 translation
[    0.248425] arm-smmu 15000000.iommu:         coherent table walk
[    0.248440] arm-smmu 15000000.iommu:         stream matching with 79 register groups
[    0.248506] arm-smmu 15000000.iommu:         106 context banks (0 stage-2 only)
[    0.250235] arm-smmu 15000000.iommu:         Supported page sizes: 0x61311000
[    0.250262] arm-smmu 15000000.iommu:         Stage-1: 48-bit VA -> 48-bit IPA
[    0.250485] arm-smmu 15000000.iommu:         preserved 0 boot mappings
[    0.432818] geni_se_qup 8c0000.geniqup: Adding to iommu group 0
[    0.436634] geni_se_qup ac0000.geniqup: Adding to iommu group 1
[    0.437611] geni_se_qup cc0000.geniqup: Adding to iommu group 2
[    0.446928] arm-smmu 2ca0000.iommu: probing hardware configuration...
[    0.446968] arm-smmu 2ca0000.iommu: SMMUv2 with:
[    0.447027] arm-smmu 2ca0000.iommu:  stage 1 translation
[    0.447059] arm-smmu 2ca0000.iommu:  non-coherent table walk
[    0.447091] arm-smmu 2ca0000.iommu:  (IDR0.CTTW overridden by FW configuration)
[    0.447133] arm-smmu 2ca0000.iommu:  stream matching with 4 register groups
[    0.447190] arm-smmu 2ca0000.iommu:  5 context banks (0 stage-2 only)
[    0.447240] arm-smmu 2ca0000.iommu:  Supported page sizes: 0x61311000
[    0.447282] arm-smmu 2ca0000.iommu:  Stage-1: 48-bit VA -> 48-bit IPA
[    0.447490] arm-smmu 2ca0000.iommu:  preserved 0 boot mappings