# Pastebin e0f21Yiy
apalos: ellesmere:~/u$ ub-pyt coral tpm
+u-boot-test-flash chromebook_coral coral
+u-boot-test-reset chromebook_coral coral
{lab mode}
Building U-Boot in pytest-source dir for chromebook_coral
Bootstrapping U-Boot from dir /tmp/b/chromebook_coral
Writing U-Boot using method em100

{lab ready in 24.6s: U-Boot 2025.04-rc5-00708-g4b7321620366 (Apr 01 2025 - 15:23:30 -0600)}
=> tpm2 autostart                             
=> => echo $?
0
=> .=> tpm2 startup TPM2_SU_CLEAR
=> => echo $?
0
=> .=> tpm2 self_test full
=> => echo $?
0
=> .=> tpm2 self_test continue
=> => echo $?
0
=> .=> tpm2 clear TPM2_RH_LOCKOUT
=> => echo $?
0
=> => tpm2 clear TPM2_RH_PLATFORM
=> => echo $?
0
=> .=> tpm2 autostart
=> => echo --- start of init ---
--- start of init ---
=> => tpm2 clear TPM2_RH_LOCKOUT
=> => echo $?
0
=> => echo --- end of init ---
--- end of init ---
=> => tpm2 change_auth TPM2_RH_LOCKOUT unicorn
=> => echo $?
0
=> => tpm2 clear TPM2_RH_LOCKOUT unicorn
=> => echo $?
0
=> => tpm2 clear TPM2_RH_PLATFORM
       cr50_i2c_read() Read response failed (err=-121)
Timed out waiting for bus
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
       cr50_i2c_read() Address write failed (err=-121)
=> .s=> tpm2 autostart
=> => echo --- start of init ---
--- start of init ---
=> => tpm2 clear TPM2_RH_LOCKOUT
=> => echo $?
0
=> => echo --- end of init ---
--- end of init ---
=> => bdinfo
boot_params = 0x00000000
DRAM bank   = 0x00000000
-> start    = 0x00000000
-> size     = 0x7ac00000
DRAM bank   = 0x00000001
-> start    = 0x100000000
-> size     = 0x80000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 115200 bps
relocaddr   = 0x79b5f000
reloc off   = 0x78a4f000
Build       = 32-bit
current eth = unknown
eth-1addr   = (not set)
IP addr     = <NULL>
fdt_blob    = 0x77b3ad00
Video       = gma@2,0 active
FB base     = 0x79c00000
FB copy     = 0xb0000000
 copy size  = 0x00000000
FB size     = 1024x768x32
lmb_dump_all:
 memory.count = 0x3
 memory[0]	[0x0-0x9ffff], 0xa0000 bytes, flags: none
 memory[1]	[0x100000-0xfffffff], 0xff00000 bytes, flags: none
 memory[2]	[0x12151000-0x7abfffff], 0x68aaf000 bytes, flags: none
 reserved.count = 0x1
 reserved[0]	[0x76b08fd0-0x7abfffff], 0x40f7030 bytes, flags: no-map
devicetree  = separate
serial addr = 0xde000000
 width      = 0x00000001
 shift      = 0x00000002
 offset     = 0x00000000
 clock      = 0x001c2000
stack ptr   = 0x77b08d2c
ram_top ptr = 0x7ac00000
malloc base = 0x77b40000
prev table  = 0x00000000
clock_rate  = 0x41351d80
tsc_base    = 0x00000000
vendor      = 0x00000001
 name       = GenuineIntel
model       = 0x0000005c
phys_addr in bits= 0x00000027
table start = 0x000f0000
table end   = 0x000f0000
 high start = 0x77b0b000
 high end   = 0x77b2e16d
tsc         = 0x8e178ee01
=> => tpm2 dam_parameters 3 10 0
do_tpm_dam_parameters() Changing dictionary attack parameters:
do_tpm_dam_parameters() - maxTries: 3- recoveryTime: 10
do_tpm_dam_parameters() - lockoutRecovery: 0
=> => echo $?
0
=> => tpm2 get_capability 0x6 0x20f 0x200000 3
Capabilities read from TPM:
Property 0x0000020f: 0x00000003
Property 0x00000210: 0x0000000a
Property 0x00000211: 0x00000000
=> => echo $?
0
=> .=> tpm2 autostart
=> => echo --- start of init ---
--- start of init ---
=> => tpm2 clear TPM2_RH_LOCKOUT
=> => echo $?
0
=> => echo --- end of init ---
--- end of init ---
=> => tpm2 pcr_read 10 0x200000
Error: 132
=> => echo $?
1
=> F+u-boot-test-reset chromebook_coral coral
{lab mode}
Building U-Boot in pytest-source dir for chromebook_coral
Bootstrapping U-Boot from dir /tmp/b/chromebook_coral
Writing U-Boot using method em100
Lab timeout: Marking connection bad - no other tests will run

=================================== FAILURES ===================================
______________________________ test_tpm2_pcr_read ______________________________
test/py/tests/test_tpm2.py:252: in test_tpm2_pcr_read
    assert output.endswith('0')
E   AssertionError: assert False
E    +  where False = <built-in method endswith of str object at 0xb447c8>('0')
E    +    where <built-in method endswith of str object at 0xb447c8> = '1'.endswith
=========================== short test summary info ============================
FAILED test/py/tests/test_tpm2.py::test_tpm2_pcr_read - AssertionError: assert False
! _pytest.outcomes.Exit: Lab timeout: Marking connection bad - no other tests will run !
1 failed, 7 passed, 1 skipped, 501 deselected in 98.11s (0:01:38)
+u-boot-test-release chromebook_coral coral
ellesmere:~/u$