# Pastebin d9lptH6H
        if synth_mode == "vivado":
            if platform.verilog_include_paths:
                tcl.append("synth_design -top {} -part {} -include_dirs {{{}}}".format(build_name, platform.device, " ".join(platform.verilog_include_paths)))
            else:
                tcl.append("synth_design -top {} -part {}".format(build_name, platform.device))
        elif synth_mode == "yosys":
            tcl.append("read_edif {}.edif".format(build_name))
            tcl.append("link_design -top {} -part {}".format(build_name, platform.device))