# Pastebin W1bTSIkW
		assigned-clocks = <&clkc CLKID_MPLL2>,
				  <&clkc CLKID_MPLL0>,
				  <&clkc CLKID_MPLL1>;
		assigned-clock-parents = <0>, <0>, <0>;
		assigned-clock-rates = <294912000>,
				       <270950400>,
				       <393216000>;