# Pastebin UCCQdBql
rom   = self.bus.slaves.pop("rom")
spram = self.bus.slaves.pop("spram")
self.bus.slaves["rom"]   = wishbone.Interface()
self.bus.slaves["spram"] = wishbone.Interface()
self.submodules.bus_interconnect = wishbone.InterconnectShared(
    masters = [self.cpu.ibus, self.bus.slaves["rom"], self.bus.slaves["spram"]],
    slaves  = [(self.bus.regions[n].decoder(self.bus), s) for n, s in {"rom": rom, "sram": spram}.items()]
)