# Pastebin OpjB3ZzD
`ifndef VCDFILE
`define VCDFILE "out.vcd"
`endif

module test;

	/* Make a regular pulsing clock. */
	reg clk = 0;
	always #2 clk = !clk;

	wire [7:0] leds;
	top t (clk, leds[2], leds[3], leds[4], leds[5]);

	initial begin
		$dumpfile(VCDFILE);
		$dumpvars(1, t);
		#9999999  $dumpflush;
		#10000000 $finish;
	end

endmodule // test