# Pastebin NU1ZcSRD

LiteDRAM testing software built Apr 28 2020 16:21:28

Available commands:
help                            - this command
reboot                          - reboot CPU
sdram                           - init and test SDRAM
RUNTIME>sdram
Initializing SDRAM...
SDRAM now under software control
Write leveling:
Command/Clk scan:
|00000000|0000|0000|0000| best: -1
Data scan:
m0: |1111111111111000000000| delay: -1
m1: |1111111111110000000000| delay: -1
m2: |1111111110000000000000| delay: -1
m3: |1111100000000000000000| delay: -1
m4: |0000000000011111111111| delay: 169
m5: |0000000000000000001111| delay: 277
m6: |1000000000000000000011| delay: 308
m7: |1000000000000000000111| delay: 302
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b0 delays: -
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b0 delays: -
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b0 delays: -
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |00000000000000000000000000000000| delays: -
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b0 delays: -
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |00000000000000000000000000000000| delays: -
m4, b5: |01111111111111111000000000000000| delays: 133+-129
m4, b6: |00000000000000000001111111111111| delays: 404+-108
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b5 delays: 134+-133
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00000000000000000000000000000000| delays: -
m5, b5: |11111111111100000000000000000000| delays: 87+-87
m5, b6: |00000000000001111111111111111000| delays: 332+-126
m5, b7: |00000000000000000000000000000000| delays: 501+-10
best: m5, b6 delays: 333+-126
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00000000000000000000000000000000| delays: -
m6, b5: |11111111000000000000000000000000| delays: 56+-56
m6, b6: |00000000011111111111111111000000| delays: 269+-128
m6, b7: |00000000000000000000000000011111| delays: 467+-44
best: m6, b6 delays: 272+-129
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00000000000000000000000000000000| delays: -
m7, b5: |11111100000000000000000000000000| delays: 38+-38
m7, b6: |00000001111111111111111000000000| delays: 229+-130
m7, b7: |00000000000000000000000001111111| delays: 450+-62
best: m7, b6 delays: 231+-132
SDRAM now under hardware control
Memtest bus failed: 80/256 errors
Memtest data failed: 262144/524288 errors
Memtest addr failed: 4096/8192 errors