# Pastebin ISAUB91o
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index c4e612e7..5df83379 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -119,7 +119,7 @@ class VexRiscv(CPU, AutoCSR):
         self.interrupt        = Signal(32)
         self.ibus             = ibus = wishbone.Interface()
         self.dbus             = dbus = wishbone.Interface()
-        self.periph_buses     = [ibus, dbus]
+        self.periph_buses     = [dbus]
         self.memory_buses     = []
 
         # # #
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 86a797fe..16d460b9 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -91,6 +91,9 @@ int main(int i, char **c)
        uart_init();
 #endif
 
+       while (1)
+               puts("h");
+
        printf("\n");
        printf("\e[1m        __   _ __      _  __\e[0m\n");
        printf("\e[1m       / /  (_) /____ | |/_/\e[0m\n");
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index ccb30e9b..9113d192 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -324,6 +324,14 @@ class SimSoC(SoCCore):
         else:
             self.comb += platform.trace.eq(1)
 
+        # Get ROM Slave interface and add a direct connection to CPU Instruction bus.
+        rom = self.bus.slaves.pop("rom")
+        self.bus.slaves["rom"] = wishbone.Interface()
+        self.submodules += wishbone.Arbiter(
+            masters  = [self.cpu.ibus, self.bus.slaves["rom"]],
+            target   = rom
+        )
+
 # Build --------------------------------------------------------------------------------------------
 
 def sim_args(parser):