# Pastebin HCYmPpaS } else if (header_type == PCI_HEADER_TYPE_PCI_BRIDGE) { // type 1 printf("primary bus=%02x secondary=%02x subordinate=%02x\n", config.type1.primary_bus, config.type1.secondary_bus, config.type1.subordinate_bus); for (i=0; i < 2; i+=2) { printf("bar%d=%08x bar%d=%08x\n", i, config.type1.base_addresses[i], i+1, config.type1.base_addresses[i+1]); } printf("mem base=%08x mem limit=%08x\n", config.type1.memory_base << 16, (config.type1.memory_limit << 16) | 0xf'ffff); switch ((config.type1.io_base & 0xf)) { case 0: // 16 bit io addressing printf("io base=%04x io limit=%04x\n", (config.type1.io_base % 0xf0) << 8, ((config.type1.io_limit & 0xf0) << 8) | 0xfff ); break; case 1: // 32 bit io addressing printf("io base=%08x io limit=%08x\n", (config.type1.io_base % 0xf0) << 8 | config.type1.io_base_upper << 16, ((config.type1.io_limit & 0xf0) << 8) | 0xfff | config.type1.io_limit_upper << 16); break; } switch ((config.type1.prefetchable_memory_base & 0xf)) { case 0: // 32 bit prefetchable addressing printf("prefetchable base=%08x prefetchable limit=%08x\n", (config.type1.prefetchable_memory_base & 0xfff0) << 16, (config.type1.prefetchable_memory_limit & 0xfff0) << 16 | 0xf'ffff); break; case 1: // 64 bit prefetchable addressing printf("prefetchable base=%llx prefetchable limit=%llx\n", ((uint64_t)config.type1.prefetchable_memory_base & 0xfff0) << 16 | ((uint64_t)config.type1.prefetchable_base_upper << 32), ((uint64_t)config.type1.prefetchable_memory_limit & 0xfff0) << 16 | 0xf'ffff | ((uint64_t)config.type1.prefetchable_limit_upper << 32)); break; }