# Pastebin DAxykk5l
@@ -105,6 +105,9 @@ class BaseSoC(SoCCore):
         if 'integrated_sram_size' not in kwargs:
             kwargs['integrated_sram_size']=0x2800
 
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_usb_48 = ClockDomain()
+
         # FIXME: Force either lite or minimal variants of CPUs; full is too big.
 
         platform.add_extension(serial)