# Pastebin 4LJJZHcI
        2>&1 | tee -a /usr/local/google/home/tansell/github/timvideos/litex-buildenv/build/tinyfpga_bx_usbtest_picorv32.minimal//output.20181125-143951.log; (exit ${PIPESTATUS[0]})
Traceback (most recent call last):
  File "./make.py", line 164, in <module>
    main()
  File "./make.py", line 148, in main
    vns = builder.build(**dict(args.build_option))
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
    toolchain_path=toolchain_path, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
    return self.platform.build(self, *args, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
    v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
    **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
    create_clock_domains=False, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/gen/fhdl/verilog.py", line 407, in convert
    ns, r.add_data_file, attr_translate)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/litex/litex/gen/fhdl/verilog.py", line 336, in _printspecials
    pr = call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/migen/migen/fhdl/tools.py", line 333, in call_special_classmethod
    return getattr(cl, method)(obj, *args, **kwargs)
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/migen/migen/fhdl/specials.py", line 343, in emit_verilog
    r += "always @(posedge " + gn(port.clock) + ") begin\n"
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/migen/migen/fhdl/specials.py", line 320, in gn
    return verilog_printexpr(ns, e)[0]
  File "/usr/local/google/home/tansell/github/timvideos/litex-buildenv/third_party/migen/migen/fhdl/verilog.py", line 117, in _printexpr
    raise TypeError("Expression of unrecognized type: '{}'".format(type(node).__name__))
TypeError: Expression of unrecognized type: 'ClockSignal'

real    0m0.524s
user    0m0.450s
sys     0m0.033s
Makefile:256: recipe for target 'gateware' failed
make: *** [gateware] Error 1