# Pastebin 1AIrGhDw
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   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 30 2020 19:21:38
 BIOS CRC passed (f14ae397)

 Migen git sha1: 5b5e4fd
 LiteX git sha1: b82b3b7

--=============== SoC ==================--
CPU:       VexRiscv @ 125MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  1048576KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Write leveling:
Command/Clk scan:
|11111111000000000001111111111111| best: 21
Data scan:
m0: |00000111111111111000000000| delay: 05
m1: |00000011111111111100000000| delay: 06
m2: |00011111111111100000000000| delay: 03
m3: |00011111111111100000000000| delay: 03
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b0 delays: -
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b0 delays: -
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b0 delays: -
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |00000000000000000000000000000000| delays: -
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b0 delays: -
SDRAM now under hardware control
Memtest bus failed: 106/256 errors
Memtest data failed: 524278/524288 errors
Memtest addr failed: 8192/8192 errors
Memory initialization failed

--============= Console ================--
litex> help
LiteX BIOS, available commands:
mr         - read address space
mw         - write address space
mc         - copy address space

crc        - compute CRC32 of a part of the address space
ident      - display identifier

flush_cpu_dcache - flush CPU data cache
flush_l2_cache   - flush L2 cache

reboot     - reset processor
serialboot - boot via SFL

memtest    - run a memory test

litex>